Article ID: 000076113 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Can I use existing Synopsys Design Compiler (DC) ASIC synthesis scripts for FPGA synthesis in the DC FPGA software?

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Description The DC FPGA software accepts Design Compiler Tcl scripts without modification. However, not all Design Compiler constraints are supported or necessary for FPGA synthesis, and these constraints are ignored by the DC FPGA software.

For a list of supported constraints, see the Synopsys DC FPGA Support chapter in Volume 1 of the Quartus II Handbook

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Intel® Programmable Devices

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