Article ID: 000075966 Content Type: Product Information & Documentation Last Reviewed: 06/30/2014

How long should I wait between subsequent transceiver dynamic reconfiguration Avalon Memory Mapped processes on Stratix V and Arria V transceiver devices?

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Description When you start a transceiver dynamic reconfiguration processes on Stratix® V and Arria® V transceiver devices, the Reconfiguration Controller "busy" signal will assert high within 3 "mgmt_clk_clk" cycles. You should wait until after the Reconfiguration Controller "busy" signal goes low again before starting the next process.

Related Products

This article applies to 7 products

Arria® V SX SoC FPGA
Arria® V ST SoC FPGA
Arria® V GZ FPGA
Arria® V GX FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA

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