Article ID: 000075961 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Should Gate Level Simulation be used to verify an AltMemPhy based External Memory interface?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description
Altera® recommends that users validate the timing of their design using TimeQuest Timing Analysis and not via gate level simulation.
For AltMemPhy® designs Altera recommends functional verification via RTL simulation and timing verification via TimeQuest timing analysis.

Related Products

This article applies to 6 products

HardCopy™ III ASIC Devices
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Stratix® II GX FPGA
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Stratix® III FPGAs
Cyclone® III FPGAs