Article ID: 000075870 Content Type: Troubleshooting Last Reviewed: 11/18/2011

Minimum Pulse Width Timing Failures for UniPHY External Memory Interfaces

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Designs targeting Stratix V devices at speeds greater than 500MHz might experience minimum pulse width timing failure.

    Resolution

    There is no workaround for this issue.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

    Need more help?

    Contact support

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.