U-Boot Times Out During FPGA Programming

On the Cyclone V SoC HPS, U-Boot might time out without completing, and report an error code of -6, indicating that the FPGA control block cannot obtain valid data. This can happen if the FPGA manager exits the initialization phase before U-Boot tests for it. As a result, the value of the FPGA manager’s stat.mode field is USERMODE, and U-Boot times out waiting for stat.mode to be set to INITPHASE.

Edit the U-Boot source file arch/arm/cpu/armv7/socfpga/fpga_manager.c. Modify the stat.mode test to allow either stat.mode = INITPHASE or stat.mode = USERMODE.

Alternatively, upgrade to v13.1 or later.