Article ID: 000075853 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Can I use any dedicated clock pin as the input clock source for fast PLLs in Stratix and Stratix GX devices?

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Description Yes, you can use any dedicated clock pin as the input clock source for fast PLLs in Stratix® and Stratix GX devices. However, the clock delay from the input clock pin to the clock port of the PLL will only be properly compensated if the clock port is fed by the dedicated input pin closest to the PLL. Refer to the Stratix Clock Input Sources for Enhanced & Fast PLLs in General-Purpose PLLs in Stratix and Stratix GX Devices (PDF) to determine which dedicated input clock pin drives specific PLLs.

If the fast PLL gets its input clock from another dedicated clock pin, which does not directly feed the fast PLL, the clock signal is first routed onto a global clock network and then drives into the PLL. In this case, the clock delay will not be fully compensated.

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Stratix® FPGAs