Why is my Stratix IV GX/GT system exhibiting receiver bit errors when using dynamic reconfiguration to change between PCIe mode and any other transceiver mode?

For information on why your Stratix® IV system may exhibit receiver bit errors using dynamic reconfiguration to change between PCIe mode and any other transceiver mode, refer to the Stratix IV GX Errata Sheet (PDF) and Stratix IV GT Errata Sheet (PDF).

To resolve the problem, apply the reset sequence solution described below and illustrated in the waveforms in Figure 1 after dynamic reconfiguration is completed. Applying the reset sequence ensures each transceiver is initialized correctly.

Figure 1. Reset Sequence Waveform

Assert the rx_analogreset and the rx_digitalreset signals.

1. The rx_freqlocked[0..n-1] signals will go low, indicating that the transceivers are locking to the reference clock (lock to reference).
2. Deassert the rx_analogreset signal. Ensure data is present at the receiver inputs before deasserting the rx_analogreset signal.
3. The rx_freqlocked[0..n-1] signals will go high, indicating the transceivers are locking to data.
4. About 4 µs (t_{LTD_Auto}) after the last rx_freqlocked signal goes high, deassert the rx_digitalreset signal.