Why does the Multi Channel DMA IP for PCI Express* for P-Tile, have incorrect bus width for the Config TL Interface?

Due to a problem with the Multi Channel DMA IP for PCI Express* for P-Tile, in the Intel® Quartus® Prime Pro Edition software version 21.1 , the Config TL Interface reports incorrect widths.

The usr_hip_tl_config_func_o signal should be a 3-bit signal, and the usr_hip_tl_config_ctl_o signal should be a 16-bit signal. 

This problem is fixed starting in the Intel® Quartus® Prime Pro Edition software revision 21.2.

The Multi Channel DMA IP for PCI Express* user guide is scheduled to be fixed in a future release of the document.