The Intel® Stratix® 10 E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example is not functional in hardware.

The Intel® Stratix® 10  E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example available in the Intel® Quartus® Prime Pro Edition Software versions 21.1 supports simulation using the provided testbench in both Synopsys* VCS* and Mentor* Modelsim.

Hardware test is not supported in version 21.1 of the Intel® Quartus® Prime Software.

The timing analyzer may report timing violations when compiling the example design in version 21.1 of the Intel® Quartus® Prime Software.

To work around this problem in Intel® Quartus® Prime Pro Edition Software version 21.1, install the patch below:

Download the version 21.1 patch 0.15 for Linux (.run)

Download the version 21.1 patch 0.15 for Windows* (.exe)

Download the Readme for version 21.1 patch 0.15 (.txt)

This problem is fixed starting with the Intel® Quartus® Prime Pro Software version 21.3.

A patch for version 21.2 of the  Intel® Quartus® Prime Pro Software is available from the link below:

Why does the Intel® Stratix® 10 E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example generation fail?