How do I address hold time violations for paths where the destination register is implemented inside a dedicated DSP block in Arria® V devices?

Due to a problem in the Quartus® II software version 13.1 and earlier, you may see hold violations in Arria® V designs for paths where the source register is implemented using a standard core register and the destination register is implemented as a dedicated DSP input register.

To work around this problem, overconstrain the hold requirements during the fitting process by adding this constraint to your Synopsys Design Constraints (.sdc) file:

if {($::quartus(nameofexecutable) == "quartus_map") || ($::quartus(nameofexecutable) == "quartus_fit")} {
set_min_delay -from [get_keepers {<sourece register>}] -to [get_keepers {<destination register>}] 0.1
}

If the violations you are seeing are greater than 100 ps, then the over-constraint value can be increased.

This issue has been fixed starting Quartus® II software version 13.1.2