Article ID: 000075530 Content Type: Troubleshooting Last Reviewed: 12/18/2018

Why does the High Speed Intel® Reed Solomon FPGA IP Core generate an incorrect set of check symbols for my data?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Intel® FPGA IP High-Speed Reed-Solomon Encoder/Decoder IP-RSCODEC-HS
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the RTL source generation of the High Speed Intel® Reed Solomon FPGA IP Core, if the 'Hyper-optimization' parameter is set to 'High' the IP will generate an incorrect set of check symbols for the incoming data payload.
     

    Resolution

    To work around this problem, set the 'Hyper-optimization' parameter to 'Low'.

    This problem is schedule to be fixed on a future release of the High Speed Intel® Reed Solomon FPGA IP Core.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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