Description
Due to a problem with the RTL source generation of the High Speed Intel® Reed Solomon FPGA IP Core, if the 'Hyper-optimization' parameter is set to 'High' the IP will generate an incorrect set of check symbols for the incoming data payload.
Resolution
To work around this problem, set the 'Hyper-optimization' parameter to 'Low'.
This problem is schedule to be fixed on a future release of the High Speed Intel® Reed Solomon FPGA IP Core.