Article ID: 000075497 Content Type: Troubleshooting Last Reviewed: 10/23/2018

Why am I writing and reading back incorrect values when accessing the transceiver PMA & PCS registers within the Intel® Stratix® 10 Low Latency 40G Ethernet Design Example?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Low Latency 40G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
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    Description

    Due to a problem in the Intel® Quartus® Prime software version 18.1, writes to the transceiver PMA and PCS registers within the Intel® Stratix® 10 Low Latency 40G Ethernet Design Example will not take effect. In addition, reads from the transceiver PMA and PCS registers within the Intel Stratix 10 Low Latency 40G Ethernet Design Example will return incorrect values.  

    Resolution

    This problem is scheduled to be fixed in a future release of the Intel Quartus Prime software.

    Related Products

    This article applies to 4 products

    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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