Article ID: 000075449 Content Type: Troubleshooting Last Reviewed: 03/24/2023

Why do I get three unconstrained clocks in the Timing Analyzer for my DDR3 controller in Arria® V devices?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 12.0sp2 and later, three unconstrained clocks might appear in the Timing Analyzer when creating a DDR3 controller with UniPHY for Arria® V ST, GX, and GT devices. The clock output pin names end with the following:

    <hierarchy>|dqs_enable_ctrl~DFFEXTENDDQSENABLE

    Resolution

    These unconstrained clocks can safely be ignored. This problem has been fixed in the Intel® Quartus® Prime Edition Software version 13.1.

    Related Products

    This article applies to 3 products

    Arria® V GX FPGA
    Arria® V GT FPGA
    Arria® V ST SoC FPGA

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