Article ID: 000075428 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Would the simulation show correct lock time for the PLL implemented in the device?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, a realistic PLL lock time is not modeled in any simulation software. The simulation will show a significantly faster lock time. Refer to the device datasheet for the actual lock time specification.

Related Products

This article applies to 9 products

HardCopy™ III ASIC Devices
Cyclone® III FPGAs
Stratix® GX FPGA
Cyclone® II FPGA
Arria® GX FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Cyclone® FPGAs
Stratix® III FPGAs

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