Article ID: 000075422 Content Type: Troubleshooting Last Reviewed: 11/27/2024

Why does the Stratix® 10 100G Ethernet Soft IP core fail timing closure for ES devices?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Low Latency 100G Ethernet Intel® FPGA IP for Arria® 10 and Stratix® V
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    For non-production (ES) Stratix® 10 devices, e.g. 1SG280HU2F50E2VGS1, timing closure may not be achieved for all seeds.

    Resolution

    Please seed sweep to achieve timing closure.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 GX FPGA

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