Article ID: 000075406 Content Type: Troubleshooting Last Reviewed: 02/17/2023

Why do I see redundant lvds_clk and loaden output ports when using IOPLL IP for LVDS external PLL mode?

Environment

  • Intel® Quartus® Prime Pro Edition
  • PLL
  • IOPLL Intel® FPGA IP
  • LVDS SERDES Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Software version 17.1, generation of the IOPLL IP for external PLL LVDS mode results in two lvds_clk and loaden output ports. 

    If the enable LVDS_CLK/LOADEN0 option is on, the RTL incorrectly includes five output ports.

     

     

    Resolution

    This problem is fixed starting with the Intel® Quartus® Prime Pro/Standard Edition Software version 19.3.

    Related Products

    This article applies to 2 products

    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 SX SoC FPGA

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