Critical Issue
Description
The frequency of coreclkout is reported incorrectly
for the Stratix V Hard IP for PCI Express IP Core when the ATX PLL
is used in Gen1 and Gen2 ES devices. For Gen2 ES variants, the frequency
that the Quartus II software reports for coreclkout is
one half the actual frequency. For Gen1 ES variants, the frequency
that the Quartus II software reports for coreclkout is one quarter
the actual frequency
Resolution
This issue is fixed in version 12.1 of the Stratix V Hard IP for PCI Express IP Core.