Description
Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error if your Arria® V design includes the Altera® Serial Digital Interface (SDI) II Megacore® IP.
The error occurs when Tx PLL Dynamic Switching is enabled and xcvr_refclk and xcvr_refclk_alt are driven by the same clock source.
Resolution
To work around this problem, ensure that xcvr_refclk and xcvr_refclk_alt are driven by different sources.
Future versions of the Quartus II software are scheduled to support xcvr_refclk and xcvr_refclk_alt being driven by the same source.