Description
For Stratix™ and Stratix™ GX devices, the project clock settings override the PLL settings. This problem with reported I/O times may occur if you change the input clock frequency setting for a PLL through the Settings dialog box, when the PLL is configured to provide a phase shift. The Quartus® II software will not recalculate the phase shift delay in this case when performing timing analysis. This problem could affect the I/O times reported during timing alanysis.
To avoid this problem, rerun the fitter before performing a timing analysis with the changed input clock frequency.
This problem is scheduled to be fixed in a future version of the Quartus II software.