When expanding the above error message in the Quartus® II software, you might get the following error message when targeting a Stratix® V, Arria® V, and Cyclone® V device:
Error (177020): The PLL reference clock input pin <pin name> was not placed in a dedicated input pin that can reach fractional PLL <PLL name>
This error message pair is generated when trying to directly feed a fractional PLL with a CLKn pin.
Place a clock contol block (ALTCLKCTRL megafunction) between the CLKn pin and the input port of the PLL as shown in the example below:
Example: