Article ID: 000074898 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Why do I see minimum pulse width timing violations for Stratix IV GT devices from the receiver to the FPGA core interface for data rates greater than 10Gbps?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This timing violation will be reported by Timequest® and is due to a problem in the Quartus® II software version 9.0 SP2 when using Stratix® IV GT devices.

    This is a software issue, Stratix IV GT devices work as expected in silicon and you may ignore these timing violations.

    Stratix IV GX devices are not affected.

    This problem is scheduled to be fixed in a future version of the Quartus II software.

    Related Products

    This article applies to 2 products

    Stratix® IV FPGAs
    Stratix® IV GT FPGA

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