Article ID: 000074869 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Why do I see new timing violations for transfers between 10G PCS and the core in the Quartus II software version 12.0?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description In the Quartus® II software version 12.0, timing analysis may show new paths failing between the 10G PCS and core. These paths may not have shown failures for the same design compiled using earlier versions of the Quartus II software.
Resolution These failures may be caused by cross-clock domain transfers. It may not be possible to deterministically close timing. Therefore, if these transfers need to take place successfully, insert synchronization registers or FIFOs. Otherwise, if the clock groups are asynchronous or mutually exclusive, these paths can be cut from the timing analysis in your Synopsys Design Constraints (.sdc) file.

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