Article ID: 000074854 Content Type: Troubleshooting Last Reviewed: 03/22/2019

Why is there a difference in I/O pin counts for Cyclone® V GX C5 and C7 devices with package F672 in Cyclone V Device Handbook and Cyclone V Device Pin-Out Files?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a bug in the Cyclone® V Device Handbook the number of I/O pin counts are wrongly given in bank 5B and 6A for Cyclone® V GX C5 and C7 devices with package F672.

    Resolution

    As a workaround, you can derive the correct number of I/O pins for Cyclone V GX C5 and C7 devices from the respective Cyclone V Device Pin-Out Files.

    Related Products

    This article applies to 1 products

    Cyclone® V GX FPGA

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