Due to enhancements made to SDM Mailbox Client IPs used by Intel® Stratix® 10 devices in Intel® Quartus® Prime Pro edition version 19.2, a design compiled in Intel® Quartus® Prime Pro edition version 19.2 requires using Intel® Quartus® Programmer or Programming File Generator from Intel® Quartus® Prime Pro edition version 19.2 to generate the final programming bitstream.
This includes the following IPs:
· Advanced SEU Detection Intel® Stratix® 10 FPGA IP
· Chip ID Intel® Stratix® 10 FPGA IP
· Mailbox Client Intel® Stratix® 10 FPGA IP
· Partial Reconfiguration Controller Intel® Stratix® 10 FPGA IP
· Partial Reconfiguration External Configuration Controller Intel® Stratix® 10 FPGA IP
· Intel® Stratix® 10 Serial Flash Mailbox Client Intel® FPGA IP
· Temperature Sensor Intel Intel® Stratix® 10 FPGA IP
· Voltage Sensor Intel® Stratix® 10 FPGA IP
If any of these IPs are in your design and that design is compiled with Intel® Quartus® Prime Pro edition version 19.2, and Quartus Programmer or Programming File Generator from Intel® Quartus® Prime Pro edition version 19.1 or earlier are used to create a configuration bitstream, the above error message will be seen.
To work around this problem, use Intel® Quartus® Programmer or Programming File Generator from Intel® Quartus® Prime Pro version 19.2 if your design contains any SDM Mailbox Client IPs and was compiled in Intel® Quartus® Prime Pro Edition version 19.2.