Critical Issue
The Nios II Processor Control Unit design example does not generate the required XML file in the debug STP directory (<example_design_directory>/ed_nios/jesd204b_ed_qsys/altera_jesd204_tx_mlpcs_160/synth/debug/stp). Both the TCL and XML files are required for SignalTap (STP) file generation but the debug STP directory contains only the build_stp.tcl file.
The RTL State Machine Control Unit design example and standalone JESD204B IP core generation are not impacted.
Generate a standalone JESD204B IP core with the following parameter settings:
Wrapper Options: Both Base and Phy
Data Path: Duplex
The debug STP directory of the IP core you generate should include both the build_stp.tcl and jesd204b_base_phy_duplex.xml files.
You can also refer to the steps outlined in the JESD204B IP Core User Guide, "Creating a SignalTap II Debug File to Match Your Design Hierarchy" topic. When generating the STP file in the design example debug STP directory, point the XML file input switch -xml_file to your standalone JESD204B IP core debug STP directory (<ip_variant_name>/altera_jesd204_tx_mlpcs_160/synth/debug/stp/jesd204b_base_phy_duplex.xml).
This issue will be fixed in a future release.