Description
The routing delay of scanclk from the logic array to the PLL can be greater than the routing delay of scandata from the logic array to the PLL. Therefore, you must protect your design against a positive hold time. Clocking scandata off the falling edge of scanclk will protect against a positive hold time by giving a half cycle setup time and a half cycle hold time. The Quartus® II timing analyzer does not detect the inversion on scanclk when fed by altpll_reconfig.
In order to prevent the Quartus II timing analyzer from reporting hold time violations with the altpll_reconfig megafunction, make an inverted clock setting on the scan-register fed by scanclk.
For more information on making clock settings, refer to the TimeQuest Timing Analyzer (PDF) chapter or the Classic Timing Analyzer (PDF) chapter in volume 3 of the Quartus II handbook.