Article ID: 000074678 Content Type: Troubleshooting Last Reviewed: 03/11/2013

Why does Design Space Explorer only show two effort levels for performance optimization?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in the Quartus® II software version 12.0 SP2 and earlier, Design Space Explorer (DSE) may only show two available effort levels when optimizing for performance. There should be five available effort levels. This problem affects designs targeting Arria® V, Cyclone® IV, and Cyclone V devices.
    Resolution

    To fix this problem, download and install patch 2.19 from the links below. For designs targeting Arria V or Cyclone V devices, this fix is also included in device patch 2.dp3 or later from the related solution below. You must install the Quartus II software version 12.0 SP2 before installing either of these patches.

    This problem is fixed beginning with the Quartus II software version 12.1.

    Related articles

    Related Products

    This article applies to 12 products

    Cyclone® V GT FPGA
    Cyclone® IV GX FPGA
    Arria® V GT FPGA
    Cyclone® V GX FPGA
    Cyclone® IV E FPGA
    Cyclone® V E FPGA
    Arria® V GX FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA

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