Article ID: 000074672 Content Type: Troubleshooting Last Reviewed: 02/14/2023

What are the timing parameters for the External Host interface using Partial Reconfiguration in Intel® Stratix® 10 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Partial Reconfiguration External Configuration Controller Stratix® 10 Intel® FPGA IP
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    Description

    If you intend to use External Host for Partial Reconfiguration in Intel® Stratix® 10 devices, use the Partial Reconfiguration External Configuration Controller Stratix 10 Intel FPGA IP. This IP reserves dedicated configuration pins for partial reconfiguration during user mode according to your configuration scheme.
     

    Resolution

    If you choose Active Serial x4 Configuration scheme, you must consider AS Configuration Timing parameters from the Intel® Stratix® 10 Device Datasheet. 

    If you choose AVST x8/16/32 Configuration scheme, you must consider Avalon® Streaming Configuration Timing parameters from the Intel® Stratix® 10 Device Datasheet.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs