This warning is seen when the SEU Diagnostic IP core included with the Functional Safety Data Pack (FSDP) is used in the Stratix® III, Cyclone® IV E, and Cyclone® IV GX FPGA designs with the Error Check Frequency Divisor set to a value other than 1.
Affected Quartus® II software versions are 11.0 SP1 and 14.1SP1.
The Quartus II software reports this as a warning because the cyclic redundancy check (CRC) frequency divisor parameter set in the Device and Pin options is not connected to the CRCBLOCK inside the IP core. Therefore, the SEU Diagnostic IP defaults to a value of 1 for the divisor.
When instantiating the SEU Diagnostic IP core with HDL files, go to dip_seu_check.v and replace the below mentioned lines with updated code for the Quartus® II software versions 11.0 SP1 and 14.1 SP1 respectively.
When instantiating the SEU Diagnostic IP core from the Platform Designer, update the code as mentioned below and ensure that the IP is not regenerated during compilation such that the source code is not reverted back to the original state.
| For Quartus® II software version 11.0 SP1 | ||
|---|---|---|
| Line No | Existing Code | Replace with |
| Line 183 | // stratix_crcblock crcblock ( | // stratix_crcblock # ( .oscillator_divider (*) ) crcblock ( |
| Line 193 | // stratixiii_crcblock crcblock ( | // stratixiii_crcblock # ( .oscillator_divider (*) ) crcblock ( |
| For Quartus® II sofware version 14.1 SP1 | ||
| Line 210 | // cycloneive_crcblock crcblock ( | // cycloneive_crcblock # ( .oscillator_divider (error_check_frequency_divisor) ) crcblock ( |
| Line 220 | // cycloneiv_crcblock crcblock ( | // cycloneive_crcblock # ( .oscillator_divider (error_check_frequency_divisor) ) crcblock ( |
* denotes any legally permited CRC Error Check Frequency Divisor value supported by the relevant family and specified in the user guide.
This will be fixed in a future release of Intel® Quartus® Prime Software.