Yes, there is a problem with the power estimation tools for I/O power in Cyclone® IV devices. Both the Early Power Estimator (EPE) and the Quartus® II PowerPlay Power Analyzer will not report the power consumption for off-chip termination resistors which are required for SSTL and HSTL I/O standards.
In order to estimate the current draw through off-chip termination resistors when using voltage referenced standards such as SSTL and HSTL, you can run an IBIS simulation based on your board topology. You should select the IBIS model that matches the output buffer configuration, and the input model of the far end device. If you have parallel terminations on the board, they must be included. If using on-chip or on-die termination at the far end device, be sure to select the appropriate IBIS model.
You can simulate both output driving high, and output driving low to obtain the current values, then use the average of the two current values in the equation below:
ICCIO = Output average current * number of output / bidir pins * output enable %
This ICCIO current should be considered in addition to the estimated by the EPE and the Quartus II PowerPlay Power Analyzer.