Description
If a single 4GB page is used (Fixed A2P translation table), then:
1. For 32-bit addressing the full 32-bit Avalon-MM address is the actual PCIe host address. Please leave the value in the Address translation table of the lower 32bit to default value of 0.
2. For 64-bit addressing, the full 32-bit Avalon-MM address is the lower 32-bit PCIe address, and the upper 32-bit PCIe host address is set by user in the GUI.
User sets 64-bit addressing by entering a non-zero value in the upper 32-bit address of the translation table entry. Zero value infers 32-bit addressing.
1. For 32-bit addressing the full 32-bit Avalon-MM address is the actual PCIe host address. Please leave the value in the Address translation table of the lower 32bit to default value of 0.
2. For 64-bit addressing, the full 32-bit Avalon-MM address is the lower 32-bit PCIe address, and the upper 32-bit PCIe host address is set by user in the GUI.
User sets 64-bit addressing by entering a non-zero value in the upper 32-bit address of the translation table entry. Zero value infers 32-bit addressing.