In the Quartus® II software, certain methods of applying a preserve attribute to a register in Verilog HDL code may cause the Quartus II Integrated Synthesis tool to incorrectly apply the attribute to all registers within that module. Setting the preserve attribute on all registers within a module may prevent the Quartus II Integrated Synthesis tool from inferring state machines or internal memory blocks.
In particular, this behavior occurs if you use Verilog-2001 syntax to declare an output reg port variable in the port list for your module, but use Verilog-1995 comment-style syntax to apply the preserve attribute to that port variable. For example, if the port list for a module in your Verilog HDL code contains syntax similar to the following, all registers within the module will incorrectly have the preserve attribute applied:output reg my_reg /* synthesis syn_preserve = 1 */,
To work around this problem, use Verilog-2001 attribute syntax to apply the preserve attribute when using Verilog-2001 syntax to decare variable types in your port list. For example:(* syn_preserve *) output reg my_reg,