Article ID: 000074338 Content Type: Troubleshooting Last Reviewed: 07/17/2014

Why is a global signal assignment to |s0|rst_controller|alt_rst_sync_uq1|reset_out being ignored by my UniPHY-based DDR3 controller IP?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description After the UniPHY-based DDR3 IP pin_assignments.tcl script is run and the project compiled, the Quartus® II software Ignored Assignments Fitter report incorrectly shows a global signal assignment to the reset signal <instance_name>|s0|rst_controller|alt_rst_sync_uq1|reset_out.
    Resolution This ignored global assignment is due to a legacy code assignment and can be ignored. It is planned to be fixed in a future version of the Quartus II software.

    Related Products

    This article applies to 4 products

    Stratix® V E FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Stratix® V GX FPGA

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