Article ID: 000074317 Content Type: Troubleshooting Last Reviewed: 02/14/2023

Is it possible to increase the SEU error FIFO depth when implementing the Advanced SEU Detection Intel® FPGA IP for Intel® Stratix® 10 FPGA in Off-Chip Lookup Sensitivity Processing mode?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Advanced SEU Detection Intel® FPGA IP
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    Description

    Yes, when instantiating the Advanced SEU Detection Intel® FPGA IP  for Intel® Stratix® 10 FPGA, you can use the Single Event Upset (SEU) error FIFO depth parameter to modify the size of the internal FIFO.

    Resolution

    The value on this parameter will take effect in the two implementation modes supported by the IP: On-Chip Lookup Sensitivity Processing and Off-Chip Lookup Sensitivity Processing. Information about this has been added in the Intel® Stratix® 10 SEU Mitigation User Guide starting with version 19.3.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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