Article ID: 000074233 Content Type: Troubleshooting Last Reviewed: 08/15/2018

Why are the nPERST and OSC_CLK_1 pins not listed under Transceiver pins in the Intel® Stratix® 10 GX, MX, TX, and SX Device Family Pin Connection Guidelines?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the documentation, the Intel® Stratix® 10 GX, MX, TX, and SX Device Family Pin Connection Guidelines does not include the nPERST[L,R][0:2] pins and OSC_CLK_1 pin under Transceiver section.

Resolution

If you are using transceivers in your design, make sure you are meeting the guidelines for these pins as listed in the connection guidelines under section Dedicated Configuration/JTAG Pins (OSC_CLK_1) and Optional/Dual-Purpose Configuration Pins (nPERST[L,R][0:2]). This is scheduled to be updated in a future release.

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs