Article ID: 000074208 Content Type: Troubleshooting Last Reviewed: 07/10/2015

Why do I get a fatal error when simulating Arria 10 LVDS SERDES IP in ModelSim SE version 10.3d?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in Modelsim SE version 10.3d, you may see the following error when simulating the Arria® 10  LVDS SERDES IP.

# ** Fatal: Error occurred in protected context. # Time: 0 ns Iteration: 0 Protected: /<hierarchical path to PLL>/<protected>/<protected>/<protected> File: nofile

# FATAL ERROR while loading design # Error loading design

# ** Fatal: Error occurred in protected context.

#    Time: 0 ps  Iteration: 0  Protected: /lvds_tb/i_lvds_rx/i_lvds_pll_ip/iopll_0/altera_pll_i/<protected>/<protected>/<protected>/<protected> File: nofile

# FATAL ERROR while loading design

Resolution This is fixed in version 10.4 of Modelsim SE.

Related Products

This article applies to 3 products

Intel® Arria® 10 GT FPGA
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 SX SoC FPGA