Description
In the context of HPS Boot First mode, the initial configuration of HPS EMIF I/O and loading of HPS FSBL is called "Phase 1 configuration". The subsequent configuration of FPGA core and periphery by HPS is called "Phase 2 configuration".
The Phase 1 and Phase 2 configuration files must be generated from the same Intel® Quartus® Prime version, including patches installed if applicable, otherwise configuration of Intel® Stratix® 10 devices with HPS may fail.
Resolution
The description has been added to the Intel® Stratix® 10 Hard Processor System Technical Reference Manual.