Article ID: 000074146 Content Type: Product Information & Documentation Last Reviewed: 08/23/2023

How do I insert an LVDS buffer between an Altera_PLL and ALTLVDS_RX or ALTLVDS_TX megafunction in external PLL mode for Cyclone® V, Arria® V, and Stratix® V devices?

Environment

  • Quartus® II Subscription Edition
  • PLL
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    An LVDS buffer is required to be inserted between an Altera_PLL and ALTLVDS_RX or ALTLVDS_TX mega function when used in external PLL mode for Cyclone® V, Arria® V, and Stratix® V devices when any of the following options are turned on: 

    • Enable dynamic reconfiguration of PLL
    • Enable access to dynamic phase shift ports
    • Enable physical output clock parameters

     

    Resolution

    Download this How-To document to learn how you can add an intermediate LVDS buffer between the external PLL and ALTLVDS IP.

    The How-To document references example designs which you can download in VHDL or Verilog for each of the Cyclone® V, Arria® V, and Stratix® V devices:

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    Arria® V GT FPGA
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    Arria® V GX FPGA
    Arria® V SX SoC FPGA
    Arria® V ST SoC FPGA
    Stratix® V E FPGA

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