Article ID: 000073969 Content Type: Troubleshooting Last Reviewed: 04/18/2023

What transceiver PMA blocks are used in the Intel® Arria® 10 device internal serial loopback path?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Transceiver Native PHY Intel® Arria® 10 Cyclone® 10 FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Intel® Arria® 10 transceiver internal serial loopback path includes the Variable Gain Amplifier (VGA) and Decision Feedback Equalizer (DFE) when enabled. It does not include the TX VOD, TX Pre-emphasis, RX Continuous Time Linear Equalizer (CTLE), and RX DC Gain PMA blocks.

    Resolution

    Adjusting TX VOD, TX Pre-emphasis, RX CTLE, and RX DC Gain will not affect the signal seen by the CDR when using internal serial loopback. Adjusting RX VGA and RX DFE when enabled will affect the signal seen by the CDR.

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 SX SoC FPGA
    Intel® Arria® 10 GX FPGA

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