Due to a lack of proper JTAG timing constraints, you may see the error “Couldn't grab settings for channel TX/RX/LINK|* “ in the Intel® Transceiver Toolkit when loading a design with channels on multiple tiles.
Due to the placement of the Native PHY soft logic, the issues are most commonly observed when you have multiple Native PHY instantiations on different tiles.
The solution is to constrain the reconfiguration clock fed to the reconfiguration port of the Native PHY. Then, confirm that ‘altera_reserved_tck’ and the clock connected to the reconfiguration clock port 'rcfg_clk' of the Native PHY have both been appropriately constrained and pass timing within TimeQuest.
This clock is used for the Altera Debug Mater Endpoint (ADME) logic, which Transceiver Toolkit uses to access the transceiver's CSR space. It will be automatically constrained on your behalf if you have at least one other declared clock in your design via the SDC command 'create_clock.'
To verify JTAG has been automatically constrained, look through the output of quartus_fit for this message:
"Adding default timing constraints to JTAG signals. This will help to achieve basic functionality since the user provided no such constraints."
Alternatively, you may wish to be more accurate and manually constrain the JTAG clock. To do this use, Quartus provided an SDC timing template.
- Open the SDC file with Quartus Prime Pro Edition ( File -> Open )
- Right-click in the SDC file window to pop up the menu
- Select 'Insert Template
(4). Select 'JTAG Signal Constraint' to insert constraints to the SDC file.
