Description
You may see this error when trying to configure the Intel Agilex® 7 device on the Intel Agilex® 7 FPGA F-Series Development Kit with a SOF file over JTAG when the FPGA MSEL pins are set to ASx4 mode, and the QSPI contains an image from an older version of Intel® Quartus® Prime Software than currently being used.
Resolution
To avoid this error, set the MSEL pins to JTAG only so the device does not configure from the QSPI device on power-up. On the Intel Agilex® 7 FPGA F-series Development Kit, this is achieved by setting SW1 to OFF/OFF/OFF (MSEL[2:0] = "111"). This will allow you to configure the FPGA over JTAG with a SOF file and also allow you to write a new image to the QSPI with a JIC file.