Article ID: 000073829 Content Type: Troubleshooting Last Reviewed: 08/03/2023

ncelab: *F,CUMSTS: Timescale directive missing on one or more modules

Environment

  • Quartus® II Subscription Edition
  • Arria® V GZ Hard IP for PCI Express Intel® FPGA IP
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Hard IP for PCI Express® auto-generated ncsim_setup.sh file is missing the timescale option.
    This problem can result in the Cadence® NC-Sim® simulator generating the following error during elaboration.

    ncelab: *F,CUMSTS: Timescale directive missing on one or more modules

     

    Resolution

    To work around this problem, open the ncsim_setup.sh file using a text editor and edit the following parameters:
     
    1) Find "USER_DEFINED_ELAB_OPTIONS" variable and add "-timescale 1ns/1ps" as below.

    USER_DEFINED_ELAB_OPTIONS="-timescale 1ns/1ps"

    2) Find the "USER_DEFINED_SIM_OPTIONS" variable and delete "100" from the original line as below.

    USER_DEFINED_SIM_OPTIONS="-input \"@run ; exit\""

    3) Find the following line in the "ncsim_setup.sh" script and add " define QUARTUS" to the ncvlog command.

    ncvlog     "<path>/<device>_pcie_hip_atoms_ncrypt.v" -work stratixv_pcie_hip_ver

    Example:  ncvlog  define QUARTUS "/eda/sim_lib/cadence/stratixv_pcie_hip_atoms_ncrypt.v"  -work stratixv_pcie_hip_ver

     

    Related Products

    This article applies to 11 products

    Cyclone® V SX SoC FPGA
    Cyclone® V GT FPGA
    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Cyclone® V GX FPGA
    Arria® V GZ FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V GX FPGA
    Arria® V GT FPGA

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