Article ID: 000073678 Content Type: Install & Setup Last Reviewed: 03/14/2023

Why does the c5gt_pro_goldentop.v file in the Cyclone® V GT installation kit include ground connections for the hard memory controller?

Environment

  • Quartus® II Subscription Edition
  • DDR3 SDRAM Controller with UniPHY Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see a discrepancy between the following two files in the Cyclone® V GT installation kit:

    - c5gt_pro_goldentop.v
    - c5gt_ddr3.v

    Inside the c5gt_pro_goldentop.v file, you will see a 17-bit bus ddr3a_hmc_gnd for the required ground pins in the hard memory controller.

    The c5gt_ddr3.v file does not include this bus. These ground pins are automatically added to the pin file during compilation by the Quartus® II software and are not needed in the RTL.

     

     

    Resolution

    The ddr3a_hmc_gnd output bus can be safely removed from the c5gt_pro_goldentop.v file.

    Related Products

    This article applies to 1 products

    Cyclone® V GT FPGA