Intel® Transactional Synchronization Extensions (Intel® TSX) Memory and Performance Monitoring Update for Intel® Processors

Intel Platform Update (IPU) 2021.2 and later versions include a microcode update that will impact the behavior of the Intel® Transactional Synchronization Extensions (Intel® TSX) and Performance Monitoring Unit (PMU) on the following processors:

Table 1: Processors Affected by IPU 2021.1 Changes to Intel TSX and PMU

Intel® TSX is a technology to enable hardware transactional memory. The PMU measures performance events using performance counters. For more details on Intel® TSX, refer to the Web Resources About Intel® Transactional Synchronization Extensions. For more details on the PMU, refer to the Performance Monitoring section in Intel® Software Developer’s Manual (Intel® SDM) Volume 3.

When the IPU 2021.1 and later microcode update is applied, the following changes will occur on the affected processors:

• Intel® TSX will be disabled by default.
• The processor will force abort all Restricted Transactional Memory (RTM) transactions by default.
• A new CPUID bit CPUID.07H.0H.EDX[11](RTM_ALWAYS_ABORT) will be enumerated, which is set to indicate to updated software that the loaded microcode is forcing RTM abort. Information about the CPUID instruction is in the Processor Identification and Feature Determination section in the Intel® SDM.
• On processors that enumerate support for RTM, the CPUID enumeration bits for Intel TSX (CPUID.07H.0H.EBX[11] and CPUID.07H.0H.EBX[4]) continue to be set by default after the microcode update.
• Workloads that benefited from Intel® TSX might experience a change in performance.
• System software may use the new functionality in Model-Specific Register (MSR) 0x10F TSX_FORCE_ABORT[TSX_CPUID_CLEAR] to clear the Hardware Lock Elision (HLE) and RTM bits to indicate to software that Intel® TSX is disabled.

Additionally, Intel TSX will be disabled by default in two additional CPUIDs with IPU 2021.2.

Table 2: Processors Affected by IPU 2021.2 Changes to Intel TSX

When the IPU 2021.2 microcode is loaded, the same changes which were applied to the processors in Table 1 will also apply to the processors listed in Table 2, with two differences:

• The PMU on these processors is not affected by the microcode update.
• On these processors, system software may use a bit in Model-Specific Register (MSR) 0x122, TSX_CTRL[TSX_CPUID_CLEAR], to clear the Hardware Lock Elision (HLE) and RTM CPUID bits to indicate to software that Intel TSX is disabled.

The Performance Monitoring Impact of Intel® Transactional Synchronization Extension Memory Ordering Issue (PDF) provides details about the Intel TSX and PMU behavior changes due to the updated microcode in IPU 2021.1 and later versions and is a guide for PMU driver developers and performance tool developers. Intel does not expect this microcode update to affect users who do not use the PMU, or who only use updated PMU drivers and tools. Some advanced users of performance monitoring (Perfmon) may need to change their collection scripts and methodologies. The Intel® Transactional Synchronization Extension (Intel® TSX) Disable Update for Selected Processor Technical Paper (PDF) provides details about the Intel TSX behavior changes due to the updated microcode in IPU 2021.2. These technical paper should also be reviewed by developers that use Intel® Software Guard Extensions (Intel® SGX).

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