How Does the DRAM Caching Work in Memory Mode Using Intel® Optane™ Persistent Memory?

• The memory mode of DCPMM uses DRAM to cache data from NVM. In this mode, can operating system see DRAM and how data is evicted?
• How does the DRAM caching work? Is that all done in hardware without the support of the OS?

In Memory Mode, the DRAM acts as a cache for the most frequently accessed data, while the Intel® Optane™ persistent memory (PMem) provides large memory capacity.

Cache management operations are handled by the Intel® Xeon® Scalable processor’s integrated memory controller.

When data is requested from memory, the memory controller first checks the DRAM cache, and if the data is present, the response latency is identical to DRAM. If the data is not in the DRAM cache, it is read from the Intel® Optane™ PMem with slightly longer latency.

The applications with consistent data retrieval patterns than the memory controller can predict will have a higher cache hit-rate, and should see its performance close to all-DRAM configurations, while workloads with highly random data access over a wide address range may see some performance difference versus DRAM alone.

Also, data is volatile in Memory Mode; it will not be saved in the event of power loss.

Persistence is enabled in the second mode, called App Direct.