Interface Planner and Tile Interface Planner

Interface Planner

The Interface Planner explores a device’s peripheral architecture and efficiently assigns interfaces. The Interface Planner prevents illegal pin assignments by performing fitter and legality checks in real time. This method eliminates complex error messages and the need to wait for a full compilation thereby speeding up your I/O design.

Training Course for Fast & Easy I/O System Design with Interface Planner

Learn more about the Interface Planner, an easy-to-use tool in the Intel® Quartus® Prime software. Using the power of the Fitter you can create a legal floorplan in less than a week when it used to take months. Make guaranteed legal resource location assignments interface-by-interface instead of pin-by-pin to shorten your I/O planning cycle.

Note: The Interface Planner is supported in Intel® Agilex™, Intel® Stratix® 10, and Intel® Arria® 10 FPGAs.

Tile Interface Planner

The Intel® Quartus® Prime Tile Interface Planner helps you to quickly place component IP in legal tile locations of F-tile. Tile Interface Planner is an interactive floor planning tool that simplifies legal placement of component IP on device tiles.

Using the Interface Planner for External Memory Interface Design

Watch this video to find out how to place component IP on the F-Tile available on some Intel® Agilex™ devices.

Fast & Easy IP Placement on F-Tiles with Tile Interface Planner

Tile Interface Planner displays your project component IP in a hierarchical tree view, next to a visual representation of the device tile segments. You can then locate the potential legal locations for each IP within the tile, place the IP at the location, and apply the placement constraints to the project for downstream Compiler stages.

Note: The Interface Planner is supported in Intel® Agilex™, Intel® Stratix® 10, and Intel® Arria® 10 FPGAs. The Tile Interface Planner is only available for some Intel® Agilex™ devices that have the F-Tile.

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