Tanay Karnik is a Senior Principal Engineer and Director of Strategic CAD and Heterogeneous Platforms Lab of Intel Labs. Previously he was the Director of Intel's University Research Office. He received his Ph.D. in Computer Engineering from UIUC and joined Intel in 1995. His research interests are in the areas of heterogeneous integration, small form factor systems, 3D architectures, variation tolerance, power delivery and architectures for novel devices. He has published over 120 technical papers, has 179 issued and 30 pending patents in these areas. He received an Intel Achievement Award for the pioneering work on integrated power delivery. He has presented several keynotes, invited talks and tutorials, and has served on 7 PhD students' committees. He was a member of ISSCC, DAC, ICCAD, ICICDT, ISVLSI, ISCAS, 3DIC and ISQED program committees and JSSC, TCAD, TVLSI, TCAS review committees. Tanay was General Chair of ISLPED'14, ASQED’10, ISQED'09, ISQED'08 and ICICDT'08. Tanay is an IEEE Fellow, an ISQED Fellow, an Associate Editor for TVLSI, a Senior Advisory Board Member of JETCAS, a Guest Editor for JSSC and SSCL.
Research Areas
HPC Systems
Notable Achievements
Technical Papers Published
120
Patents Received
179
Technical Papers Published
120
Patents Received
179
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