Domains Tab (View Menu) (Platform Designer)

The tab displays a list of all the Avalon^® memory mapped domains in the system, allowing you to specify interconnect parameters. When you select a domain in the tab, the corresponding selection highlights in the tab.

Click View > Domains to display this tab.

You open this tab in Platform Designer by clicking View > Interconnect Requirements.

Filter the System View tab to display a single Avalon^® domain, or multiple domains. Further filter your view with selections in the Filters dialog box.
To rename an Avalon^® memory-mapped domain, double-click the domain name. Detailed information for the current selection appears in the Avalon^® domain details pane.
On the Domain tab, specify interconnect parameters.
To enable and disable the highlighting of the Avalon^® domains in the tab, click the domain control tool at the bottom of the tab.

Table 1. Interconnect Parameters
Option	Description
Enable All Pipelinable Locations	FALSE—Default setting. The value and post-adaptation assignments control pipeline insertion. TRUE—Enables all pipeline stages within this domain. Ignores the and any post-adaptation assignment. Also disables manual removal of pipelines in the schematic. Although this setting ignores post-adaptation assignments, the assignments still remain in the design.
	Specifies the maximum number of pipeline stages that Platform Designer can insert in each command and response path to increase the f_MAX at the expense of additional latency. You can specify between 0 and 4 pipeline stages. The default value is 1. A value of 0 indicates a combinational datapath. When the value is 1 or greater, Platform Designer adds up to that number of pipeline stages at predetermined locations. If certain adapters or IP components are not present in the interconnect, or if there are not enough pipelineable locations in the interconnect, Platform Designer does not add pipeline stages in the interconnect to meet the specification. This setting is specific for each Platform Designer system or subsystem.
Clock crossing adapter type	Specifies the default implementation for automatically inserted clock crossing adapters: Handshake—This adapter uses a simple handshaking protocol to propagate transfer control signals and responses across the clock boundary. This methodology uses fewer hardware resources because each transfer is safely propagated to the target domain before the next transfer can begin. The Handshake adapter is appropriate for systems with low throughput requirements. FIFO—This adapter uses dual-clock FIFOs for synchronization. The latency of the FIFO-based adapter is a couple of clock cycles more than the handshaking clock crossing component. However, the FIFO-based adapter can sustain higher throughput because it supports multiple transactions at any given time. FIFO-based clock crossing adapters require more resources. The FIFO adapter is appropriate for memory-mapped transfers requiring high throughput across clock domains. Auto—If you select Auto, Platform Designer specifies the FIFO adapter for bursting links, and the Handshake adapter for all other links.
Automate default slave insertion	Directs Platform Designer to automatically insert a default slave for undefined memory region accesses during system generation.
Enable instrumentation	When you set this option to TRUE, Platform Designer enables debug instrumentation in the Platform Designer interconnect, which then monitors interconnect performance in the system console.
Interconnect reset source	Select Default or a specific reset signal in your design.
Burst adapter implementation	Allows you to choose the converter type that Platform Designer applies to each burst. Generic converter (slower, lower area)—default setting. Controls all burst conversions with a single converter that is able to adapt incoming burst types. This results in an adapter that has lower f_MAX, but smaller area. Per-burst-type converter (faster, higher area)—controls incoming bursts with a particular converter, depending on the burst type. This results in an adapter that has higher f_MAX, but higher area. This setting is useful when you have AXI masters or slaves and you want a higher f_MAX.
Width adapter implementation	Generic converter (slower, lower area)—Default. Controls all burst conversions with a single converter that is able to adapt incoming burst types. This results in an adapter that has lower f_MAX, but smaller area. Optimized converter (faster, higher area)—Controls incoming bursts with a particular converter, depending on the burst type. This results in an adapter that has higher f_MAX, but higher area. This setting is useful when you have AXI masters or slaves and you want a higher f_MAX.
Enable ECC protection	Specifies the default implementation for ECC protection for memory elements. FALSE—Default. Disables ECC protection for memory elements in the Platform Designer interconnect. TRUE—Enables ECC protection for memory elements. For more information about Error Correction Coding (ECC), refer to ../../led1425927225022.htm#led1425927225022.
Use synchronous reset	When set to TRUE, all registers in the interconnect use synchronous reset. Assert the reset for at least 16 cycles and start transactions 16 cycles after deassertion of the reset. This period allows all the IP components to reset and come out of the reset state. To avoid deadlocks in the interconnect, reset hosts and agents simultaneously. If hosts and agents have different resets, agents must reset only after responding to all necessary transactions. The Use synchronous reset option is enabled by default for Stratix^® 10 devices, but is disabled by default for all other devices. Enabling synchronous reset for the interconnect does not enable synchronous reset for IP components in the system. You must separately enable the synchronous reset parameter for any component.
Optimize size for Avalon Response Data Fifo	When set to TRUE, Platform Designer does not to increase the size of the Avalon^® interface slave agent’s read FIFO to the next power of 2. Enable this setting to decrease the size of the FIFO if the FIFO becomes very large.