state Definition

The Quartus^® Prime software implements a state is in a device as a pattern of 1s and 0s (bits) that are the outputs of multiple registers (collectively called a state machine state register). States can be defined in an AHDL Text Design (.tdf) File, a Vector Waveform (.vwf) File, a VHDL Design (.vhd) File, or a Verilog Design (.v) File, and are reported in the State Machines section of the Report window.