Logic Lock Region Definition

A Logic Lock region is a type of placement constraint. You can define any arbitrary region of physical resources on the target device as a Logic Lock region. When you assign nodes or entities to a Logic Lock region, you direct the Compiler to place those nodes or entities inside the region during fitting. A Logic Lock region has a fixed size and location.

The Reserved option prevents the Fitter from placing nodes not assigned to the Logic Lock region within the Logic Lock region. To support team-based design, you can reserve areas of a device by creating a reserved Logic Lock region without assigning nodes or entities to the Logic Lock region.

Logic Lock back-annotation allows you to back-annotate all nodes in a Logic Lock region. Nodes back-annotated with Logic Lock back-annotation are locked relative to the edges of the region. If you move a back-annotated region, its member nodes maintain their relative placement in the new location.

Logic Lock regions can be nested hierarchically. If you move a parent region, child regions maintain their placement relative to their parent region.

Logic Lock assignments can be exported in a Quartus^® Prime Settings File (.qsf) for reuse in other designs.

You can create a Logic Lock region without assigning nodes or entities to it. A Logic Lock region is visible in the Chip Planner and the Logic Lock Regions window until you delete it, regardless of whether any nodes are currently assigned to the Logic Lock region.